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Itanium Cache Organization

Intel’s Itanium employs three levels of cache memory, a level 1 split cache and a level 2 and 3 unified cache.
Itanium Processor Cartridge
All 3 levels of cache are on-chip with the level 3 cache serviced by a dedicated 128 bit back-side bus that runs at full processor core speed.
The level 1 cache is a split cache. The level 1 data cache is dual ported, meaning that one port services the processor while the other services the system. The data cache is 16KB in size and has a line size of 32 bytes with a load latency of two cycles. This cache only caches data for the integer unit, not the floating point unit. It is 4-way set associative, meaning one set is comprised of 4 lines and uses a write-through with no write allocation write policy. This means that only data that is used by the processor is written into cache and when change, is changed both in the cache and main memory.
The level 1 instruction cache is fully pipelined, using a 6 wide and 10 stage deep pipeline and can deliver a 32 bit line containing two instruction bundles (six instructions) every clock cycle. It is 16KB and has a line size of 32 bytes and is 4-way set associative, having four lines per set.
The unified level 2 cache is pseudo dual ported and supports concurrent accesses via banking. It is 96KB in size with a 64 byte line size. This cache is 6-way set associative with a write-through with write allocation write policy. This means it has 6 lines per set and writes changes both to cache and main memory simultaneously.
The unified level 3 cache can be 2MB or 4Mb in size. It has a line size of 64 bytes and is 4-way set associative (4 lines per set).
The Intel Itanium processor implements the MESI state protocol to maintain cache coherency. MESI stands for Modified, Exclusive, Shared and Invalid. Using this method, 2 bits are reserved to mark each cache line with one of these four states.
Modified indicates that the line in cache has been changed and needs to be written back into main memory. It is also called the dirty bit.
Exclusive indicates that the line is present only in the current cache, but matches that of main memory (i.e. clean).
Shared indicates that the current cache line may be stored in other caches on the computer.
Invalid indicates that the current line of cache is invalid and needs to be replaced by main memory (which should always be clean).
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Content adapted from “Computer Organization & Architecture: Designing for Performance 7th Edition” & “Logic and Computer Design Fundamentals